High-Level Test Synthesis from Behavioral Descriptions

A novel full design and test generation system with combined High-Level Synthesis (HLS) and automated Hierarchical Test Pattern Generation (HTPG) was developed and experimented in cooperation between Linköping University and Tallinn Technical University. The high-level synthesis is based on an internal model of Extended Timed Petri Net (ETPN) representations. In the test generator both, register-transfer (RT) and gate-level descriptions are used, and Decision diagrams (DD) are exploited as a uniform model for describing systems at both levels. In addition to synthesis tools, interfaces to behavioral and RT-level VHDL and EDIF netlist formats have been implemented. In the paper, an overview of the implementation is given and experimental data showing the viability of the approach and the efficiency of respective tools are provided.